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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        F:\job\SolidRun\CARRIER-ONE\PCB\

Design Status Report: F:\job\SolidRun\CARRIER-ONE\PCB\LogFiles\DesignStatus_07.txt

Tue May 28 10:37:32 2013

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DESIGN STATUS
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Board Size Extents  ............ 85 X 56 (mm)
Route Border Extents  .......... 83.8 X 54.8 (mm)
Actual Board Area  ............. 4,759.9999 (mm)
Actual Route Area  ............. 4,592.2399 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    9,519.9997 Sq. (mm)5,346.331 Sq. (mm)56.16 %

Pins  .......................... 974
Pins per Route Area  ........... .2121 Pins/Sq. (mm)

Layers  ........................ 2
    Layer 1 is a signal layer
        Trace Widths  .......... .1016, .2032
    Layer 2 is a signal layer
        Trace Widths  .......... .127, .2032

Nets  .......................... 260
Connections  ................... 662
Open Connections  .............. 552
Differential Pairs  ............ 30
Differential Pair Names:   CLK1_N   CLK1_P
                           CSI_CLK0M   CSI_CLK0P
                           CSI_D0M   CSI_D0P
                           CSI_D1M   CSI_D1P
                           CSI_D2M   CSI_D2P
                           CSI_D3M   CSI_D3P
                           DSI_CLK0M   DSI_CLK0P
                           DSI_D0M   DSI_D0P
                           DSI_D1M   DSI_D1P
                           LVDS0_CLK_N   LVDS0_CLK_P
                           LVDS0_TX0_N   LVDS0_TX0_P
                           LVDS0_TX1_N   LVDS0_TX1_P
                           LVDS0_TX2_N   LVDS0_TX2_P
                           LVDS0_TX3_N   LVDS0_TX3_P
                           LVDS1_CLK_NEG   LVDS1_CLK_POS
                           LVDS1_TX0_NEG   LVDS1_TX0_POS
                           LVDS1_TX1_NEG   LVDS1_TX1_POS
                           LVDS1_TX2_NEG   LVDS1_TX2_POS
                           MDI_TRXN0   MDI_TRXN1
                           MDI_TRXN2   MDI_TRXN3
                           MDI_TRXP0   MDI_TRXP1
                           MDI_TRXP2   MDI_TRXP3
                           PCIE_CRXM   PCIE_CRXP
                           PCIE_CTXM   PCIE_CTXP
                           PCIE_RXM   PCIE_RXP
                           PCIE_TXM   PCIE_TXP
                           SATA_RXN   SATA_RXP
                           SATA_TXN   SATA_TXP
                           USB_HOST_DN   USB_HOST_DP
                           USB_OTG_DN   USB_OTG_DP
                           
Percent Routed  ................ 16.62 %

Netline Length  ................ 5,743.1736 (mm)
Netline Manhattan Length  ...... 7,207.3236 (mm)
Total Trace Length  ............ 286.9419 (mm)

Trace Widths Used (mm)  ........ .1016, .127, .2032
Vias  .......................... 4
Via Span  Name                   Quantity
   1-2    022VIA_10              4

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 149
    Parts Mounted on Top  ...... 108
        SMD  ................... 92
        Through  ............... 15
        Test Points  ........... 0
        Mechanical  ............ 1
    Parts Mounted on Bottom  ... 41
        SMD  ................... 38
        Through  ............... 3
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 148
    Holes per Board Area  ...... .0311 Holes/Sq. (mm)
Mounting Holes  ................ 30

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0