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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        S:\SolidRun\mITX-CEx7-V1.0\PCB\

Design Status Report: S:\SolidRun\mITX-CEx7-V1.0\PCB\LogFiles\DesignStatus_03.txt

Mon Mar 18 09:37:36 2019

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DESIGN STATUS
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Board Size Extents  ............ 6.693 X 6.693 (in)
Route Border Extents  .......... 6.654 X 6.654 (in)
Actual Board Area  ............. 44.795 (in)
Actual Route Area  ............. 44.27 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    89.59 Sq. (in)    13.652 Sq. (in)   15.24 %

Pins  .......................... 1487
Pins per Route Area  ........... 33.59 Pins/Sq. (in)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 6, 8, 9, 10, 12, 20, 30
    Layer 2 is a Positive Plane Layer with nets
        GND
        GNDC
        (Shield Area)
        Trace Widths  .......... 25
    Layer 3 is a signal layer
        Trace Widths  .......... 20, 40
    Layer 4 is a signal layer
        Trace Widths  .......... None.
    Layer 5 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... 4.1, 20

Nets  .......................... 407
Connections  ................... 940
Open Connections  .............. 754
Differential Pairs  ............ 1
Differential Pair Names:   N17089039   N17089060
                           
Percent Routed  ................ 19.79 %

Netline Length  ................ 541.879 (in)
Netline Manhattan Length  ...... 693.755 (in)
Total Trace Length  ............ 8.61 (in)

Trace Widths Used (th)  ........ 4.1, 5, 6, 8, 9, 10, 12, 20, 25, 30, 40
Vias  .......................... 126
Via Span  Name                   Quantity
   1-6    018VIA8_sm-bot         11
          VIA18_hole8            115

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 224
    Parts Mounted on Top  ...... 201
        SMD  ................... 169
        Through  ............... 32
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 23
        SMD  ................... 23
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 23

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 335
    Holes per Board Area  ...... 7.478 Holes/Sq. (in)
Mounting Holes  ................ 25

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0