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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        H:\job\SolidRun\CARRIER-ONE\PCB\

Design Status Report: H:\job\SolidRun\CARRIER-ONE\PCB\LogFiles\DesignStatus_08.txt

Wed Jul 03 13:37:54 2013

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DESIGN STATUS
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Board Size Extents  ............ 3.35 X 2.2 (in)
Route Border Extents  .......... 3.3 X 2.16 (in)
Actual Board Area  ............. 7.38 (in)
Actual Route Area  ............. 7.12 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    14.76 Sq. (in)    7.68 Sq. (in)     52.02 %

Pins  .......................... 939
Pins per Route Area  ........... 131.92 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 4, 5, 6, 8, 9, 10, 12, 15, 20, 30, 40, 50
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... 20
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... 5
    Layer 4 is a signal layer
        Trace Widths  .......... 5, 6, 9, 10, 20, 30, 50

Nets  .......................... 213
Connections  ................... 640
Open Connections  .............. 0
Differential Pairs  ............ 34
Differential Pair Names:   CLK1_N   CLK1_P
                           CSI_CLK0M   CSI_CLK0P
                           CSI_D0M   CSI_D0P
                           CSI_D1M   CSI_D1P
                           CSI_D2M   CSI_D2P
                           CSI_D3M   CSI_D3P
                           DSI_CLK0M   DSI_CLK0P
                           DSI_D0M   DSI_D0P
                           DSI_D1M   DSI_D1P
                           LVDS0_CLK_N   LVDS0_CLK_P
                           LVDS0_TX0_N   LVDS0_TX0_P
                           LVDS0_TX1_N   LVDS0_TX1_P
                           LVDS0_TX2_N   LVDS0_TX2_P
                           LVDS1_CLK_NEG   LVDS1_CLK_POS
                           LVDS1_TX0_NEG   LVDS1_TX0_POS
                           LVDS1_TX1_NEG   LVDS1_TX1_POS
                           LVDS1_TX2_NEG   LVDS1_TX2_POS
                           MDI_TRXN0   MDI_TRXP0
                           MDI_TRXN1   MDI_TRXP1
                           MDI_TRXN2   MDI_TRXP2
                           MDI_TRXN3   MDI_TRXP3
                           N16787605   N16787608
                           N16787611   N16787614
                           N16796096   N16796138
                           N16796098   N16796136
                           PCIE_CREFCLKM   PCIE_CREFCLKP
                           PCIE_CRXM   PCIE_CRXP
                           PCIE_CTXM   PCIE_CTXP
                           PCIE_RXM   PCIE_RXP
                           PCIE_TXM   PCIE_TXP
                           SATA_RXN   SATA_RXP
                           SATA_TXN   SATA_TXP
                           USB_HOST_DN   USB_HOST_DP
                           USB_OTG_DN   USB_OTG_DP
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 277.06 (in)

Trace Widths Used (th)  ........ 4, 5, 6, 8, 9, 10, 12, 15, 20, 30, 40, 50
Vias  .......................... 421
Via Span  Name                   Quantity
   1-4    022VIA_10              421

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 143
    Parts Mounted on Top  ...... 86
        SMD  ................... 74
        Through  ............... 12
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 57
        SMD  ................... 54
        Through  ............... 3
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 540
    Holes per Board Area  ...... 73.19 Holes/Sq. (in)
Mounting Holes  ................ 21

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0