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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        D:\Job\SolidRun\CARRIER-ONE\PCB\

Design Status Report: D:\Job\SolidRun\CARRIER-ONE\PCB\LogFiles\DesignStatus_05.txt

Wed May 22 11:50:15 2013

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DESIGN STATUS
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Board Size Extents  ............ 85 X 56 (mm)
Route Border Extents  .......... 99.63 X 48.73 (mm)
Actual Board Area  ............. 4760 (mm)
Actual Route Area  ............. 4505.974 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    9520 Sq. (mm)     5358.022 Sq. (mm) 56.28 %

Pins  .......................... 974
Pins per Route Area  ........... 0.216 Pins/Sq. (mm)

Layers  ........................ 2
    Layer 1 is a signal layer
        Trace Widths  .......... 0.152, 0.229, 0.508, 0.762
    Layer 2 is a signal layer
        Trace Widths  .......... 0.152, 0.508, 0.762

Nets  .......................... 257
Connections  ................... 0
Open Connections  .............. 0
Differential Pairs  ............ 0
Percent Routed  ................ 0.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 5658.373 (mm)

Trace Widths Used (mm)  ........ 0.152, 0.229, 0.508, 0.762
Vias  .......................... 201
Via Span  Name                   Quantity
   1-2    022VIA_12              92
          022VIA                 109

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 0
    Parts Mounted on Top  ...... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 148

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 201
    Holes per Board Area  ...... 0.042 Holes/Sq. (mm)
Mounting Holes  ................ 0

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0