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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        D:\Job\forte-innov\FORTE-1\PCB\

Design Status Report: D:\Job\forte-innov\FORTE-1\PCB\LogFiles\DesignStatus_01.txt

Wed Jul 14 12:16:22 2010

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DESIGN STATUS
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Board Size Extents  ............ 3.2 X 2.62 (in)
Route Border Extents  .......... 3.38 X 3.23 (in)
Actual Board Area  ............. 8.39 (in)
Actual Route Area  ............. 10.88 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    16.77 Sq. (in)    8.02 Sq. (in)     47.79 %

Pins  .......................... 511
Pins per Route Area  ........... 46.95 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... None.
    Layer 2 is a signal layer
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... None.

Nets  .......................... 127
Connections  ................... 206
Open Connections  .............. 206
Differential Pairs  ............ 0
Percent Routed  ................ 0.00 %

Netline Length  ................ 120.57 (in)
Netline Manhattan Length  ...... 145.39 (in)
Total Trace Length  ............ 0 (in)

Trace Widths Used (th)  ........ None.
Vias  .......................... 0

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 99
    Parts Mounted on Top  ...... 61
        SMD  ................... 13
        Through  ............... 48
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 38
        SMD  ................... 38
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 88

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 163
    Holes per Board Area  ...... 19.44 Holes/Sq. (in)
Mounting Holes  ................ 4

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0