
                               Forward Annotation
                               ------------------

                        12:16 PM Tuesday, August 28, 2018
Job Name: D:\Job\SolidRun\CuBox-Pulse-Upper Rev.1.1\PCB\CuBox-Pulse-Upper Rev.1.1.pcb


Version:  01.01.00

     The PDBs listed in the project file will be searched to satisfy the parts
      requirements of the iCDB only for parts not already found in the
      Target PDB.

     The schematic source is a Keyin Netlist.
     

     Netlist has no syntax errors

     The Keyin Netlist has been read

     Target PDB Name: Work\Layout_Temp\PartsDB.pdb

     Number of Part Numbers: 27
          Part Numb: CA20001 -> Vend Part: CA20001 
          Part Numb: CA20147 -> Vend Part: CA20147 
          Part Numb: CA40005 -> Vend Part: CA40005 
          Part Numb: CA50002 -> Vend Part: CA50002 
          Part Numb: CA60008 -> Vend Part: CA60008 
          Part Numb: CA60009 -> Vend Part: CA60009 
          Part Numb: CO00053 -> Vend Part: CO00053 
          Part Numb: CO00680 -> Vend Part: CO00680 
          Part Numb: CO00703 -> Vend Part: CO00703 
          Part Numb: DI00003 -> Vend Part: DI00003 
          Part Numb: DI00235 -> Vend Part: DI00235 
          Part Numb: DI00243 -> Vend Part: DI00243 
          Part Numb: DI00244 -> Vend Part: DI00244 
          Part Numb: DI00256 -> Vend Part: DI00256 
          Part Numb: IC00930 -> Vend Part: IC00930 
          Part Numb: IC00933 -> Vend Part: IC00933 
          Part Numb: IC01181 -> Vend Part: IC01181 
          Part Numb: IN00001 -> Vend Part: IN00001 
          Part Numb: IN00098 -> Vend Part: IN00098 
          Part Numb: MCH00097 -> Vend Part: MCH00097 
          Part Numb: RE20013 -> Vend Part: RE20013 
          Part Numb: RE20014 -> Vend Part: RE20014 
          Part Numb: RE20022 -> Vend Part: RE20022 
          Part Numb: RE20401 -> Vend Part: RE20401 
          Part Numb: RE40001 -> Vend Part: RE40001 
          Part Numb: RE70002 -> Vend Part: RE70002 
          Part Numb: TR00009 -> Vend Part: TR00009 

     Number of Part Names: 0

     Number of Part Labels: 0




     52 nets were found containing 163 pins
     52 components were found

     Creating a formatted Schematic Netlist (LogFiles\SchematicNetlist.txt)...
     A formatted Schematic Netlist has been created.

     The Logic DataBase and the Schematic Design are now in sync.  Use
      Netload to bring the Component Design into sync.

     Logic Data has been successfully Compiled with no errors or warnings.
      Please proceed with your component Design.
                                     NetLoad
                                     -------

                        12:16 PM Tuesday, August 28, 2018
Job Name: D:\Job\SolidRun\CuBox-Pulse-Upper Rev.1.1\PCB\CuBox-Pulse-Upper Rev.1.1.pcb


Version:  02.11.12

	Netloading the Layout.  Unused components will be deleted.

	Unconnected pins will be set to net "(Net0)".

	Schematic reference designator changes will be forward annotated.


     "J5007" is being converted from a spare to a "MCH00097" part.

     "J5005" is being converted from a spare to a "MCH00097" part.

     "J5006" is being converted from a spare to a "MCH00097" part.

	WARNING:  "J34" is being removed from the Layout since it is no longer in the schematic.

	WARNING:  "C230" is being removed from the Layout since it is no longer in the schematic.

     The following 1 components have not been placed:

        CON9

     Netload completed successfully with 2 warning(s).
     
     Back Annotating...

  Updating Logic Database...

     Version:  99.00.05

     Writing a list of routed plane pins to Logic\rtdplane.caf.

     Finished updating the Logic Database.

     Creating a formatted Schematic Netlist (LogFiles\AfterBakAnnoNetlist.txt)...
     A formatted Schematic Netlist has been created.

     Creating a new Keyin Netlist (D:\Job\SolidRun\CuBox-Pulse-Upper Rev.1.1\PCB\Logic\CUBOX-PULSE-UPPER.kyn)
      from the Logic Database (Work\Layout_Temp\LogicDB.lgc)...
  A new Keyin Netlist has been generated.



                 Beginning Netload on the Layout Design.
           ---------------------------------------------------
	Assigned net N17160336 to a trace which was originally on net N17140625.
	Assigned net N17160336 to a via which was originally on net N17140625.
	Assigned net N17160336 to a trace which was originally on net N17140625.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a via which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a via which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a via which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a via which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a via which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a via which was originally on net GNDC.
	Assigned net V_DCJACK_NEG to a trace which was originally on net GNDC.

Some nets were completely deleted from the Layout Design....
	Deleted net N17140625, which has no pins, from the Layout Design.

Forward-Annotation on the Layout Design has been successfully completed.

There were 36 reassignments of nets.
There were 0 traces broken back.
There were 1 nets removed from the Layout Design.