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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        D:\Job\SolidRun\CuBox-Pulse-Upper Rev.1.1\PCB\

Design Status Report: D:\Job\SolidRun\CuBox-Pulse-Upper Rev.1.1\PCB\LogFiles\DesignStatus_12.txt

Tue Aug 28 14:53:42 2018

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DESIGN STATUS
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Board Size Extents  ............ 1.848 X 1.725 (in)
Route Border Extents  .......... 1.808 X 1.686 (in)
Actual Board Area  ............. 2.694 (in)
Actual Route Area  ............. 2.556 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    5.388 Sq. (in)    2.625 Sq. (in)    48.72 %

Pins  .......................... 168
Pins per Route Area  ........... 65.738 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 10, 20, 30
    Layer 2 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 5, 10, 20, 30

Nets  .......................... 52
Connections  ................... 128
Open Connections  .............. 0
Differential Pairs  ............ 8
Differential Pair Names:   C_MDI_TRXN0   C_MDI_TRXP0
                           C_MDI_TRXN1   C_MDI_TRXP1
                           C_MDI_TRXN2   C_MDI_TRXP2
                           C_MDI_TRXN3   C_MDI_TRXP3
                           MDI_TRXN0   MDI_TRXP0
                           MDI_TRXN1   MDI_TRXP1
                           MDI_TRXN2   MDI_TRXP2
                           MDI_TRXN3   MDI_TRXP3
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 33.505 (in)

Trace Widths Used (th)  ........ 5, 10, 20, 30
Vias  .......................... 103
Via Span  Name                   Quantity
   1-4    VIA18_hole8            103

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 52
    Parts Mounted on Top  ...... 19
        SMD  ................... 17
        Through  ............... 2
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 33
        SMD  ................... 30
        Through  ............... 3
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 123
    Holes per Board Area  ...... 45.654 Holes/Sq. (in)
Mounting Holes  ................ 2

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0