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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        D:\Job\SolidRun\CuBox-pulse lower Rev.1.1\PCB\

Design Status Report: D:\Job\SolidRun\CuBox-pulse lower Rev.1.1\PCB\LogFiles\DesignStatus_12.txt

Tue Aug 28 16:22:03 2018

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DESIGN STATUS
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Board Size Extents  ............ 1.929 X 1.929 (in)
Route Border Extents  .......... 1.89 X 1.89 (in)
Actual Board Area  ............. 3.557 (in)
Actual Route Area  ............. 3.401 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    7.113 Sq. (in)    3.267 Sq. (in)    45.93 %

Pins  .......................... 675
Pins per Route Area  ........... 198.47 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 8, 10, 15, 20, 40
    Layer 2 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... 5
    Layer 3 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... 5, 10, 20
    Layer 4 is a signal layer
        Trace Widths  .......... 5, 8, 10, 20, 40

Nets  .......................... 218
Connections  ................... 438
Open Connections  .............. 0
Differential Pairs  ............ 26
Differential Pair Names:   HDMI_AUXN   HDMI_AUXP
                           HDMI_CLKN   HDMI_CLKP
                           HDMI_CLKN_CN   HDMI_CLKP_CN
                           HDMI_TXN0   HDMI_TXP0
                           HDMI_TXN0_CN   HDMI_TXP0_CN
                           HDMI_TXN1   HDMI_TXP1
                           HDMI_TXN1_CN   HDMI_TXP1_CN
                           HDMI_TXN2   HDMI_TXP2
                           HDMI_TXN2_CN   HDMI_TXP2_CN
                           MDI_TRXN0   MDI_TRXP0
                           MDI_TRXN1   MDI_TRXP1
                           MDI_TRXN2   MDI_TRXP2
                           MDI_TRXN3   MDI_TRXP3
                           N17220129   N17220131
                           N17220203   N17220205
                           N17220251   N17220253
                           N17220270   N17220272
                           N17220326   N17220328
                           N17220336   N17220338
                           N17220356   N17220358
                           USB1_DN   USB1_DP
                           USB1_RXN   USB1_RXP
                           USB1_TXN   USB1_TXP
                           USB2_DN   USB2_DP
                           USB2_RXN   USB2_RXP
                           USB2_TXN   USB2_TXP
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 121.524 (in)

Trace Widths Used (th)  ........ 5, 8, 10, 15, 20, 40
Vias  .......................... 336
Via Span  Name                   Quantity
   1-4    VIA18_hole8_SM         2
          VIA18_hole8            334

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 128
    Parts Mounted on Top  ...... 116
        SMD  ................... 109
        Through  ............... 7
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 12
        SMD  ................... 11
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 376
    Holes per Board Area  ...... 105.72 Holes/Sq. (in)
Mounting Holes  ................ 2

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0