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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        D:\Job\SolidRun\CuBox 2-Upper-v1.1\PCB\

Design Status Report: D:\Job\SolidRun\CuBox 2-Upper-v1.1\PCB\LogFiles\DesignStatus_10.txt

Thu Oct 24 14:26:01 2013

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DESIGN STATUS
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Board Size Extents  ............ 1.162 X 1.725 (in)
Route Border Extents  .......... 1.114 X 1.678 (in)
Actual Board Area  ............. 1.97 (in)
Actual Route Area  ............. 1.837 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    3.941 Sq. (in)    2.119 Sq. (in)    53.78 %

Pins  .......................... 98
Pins per Route Area  ........... 53.353 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 20, 40
    Layer 2 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 5, 20

Nets  .......................... 26
Connections  ................... 74
Open Connections  .............. 0
Differential Pairs  ............ 4
Differential Pair Names:   MDI_TRXN0   MDI_TRXP0
                           MDI_TRXN1   MDI_TRXP1
                           MDI_TRXN2   MDI_TRXP2
                           MDI_TRXN3   MDI_TRXP3
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 17.528 (in)

Trace Widths Used (th)  ........ 5, 20, 40
Vias  .......................... 79
Via Span  Name                   Quantity
   1-4    022VIA_10              79

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 25
    Parts Mounted on Top  ...... 6
        SMD  ................... 1
        Through  ............... 5
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 19
        SMD  ................... 16
        Through  ............... 3
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 127
    Holes per Board Area  ...... 64.455 Holes/Sq. (in)
Mounting Holes  ................ 14

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0