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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        D:\Job\SolidRun\CuBox 2-Lower-v1.1\PCB\

Design Status Report: D:\Job\SolidRun\CuBox 2-Lower-v1.1\PCB\LogFiles\DesignStatus_10.txt

Thu Oct 24 11:31:07 2013

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DESIGN STATUS
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Board Size Extents  ............ 1.929 X 1.929 (in)
Route Border Extents  .......... 1.899 X 1.899 (in)
Actual Board Area  ............. 3.553 (in)
Actual Route Area  ............. 3.434 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    7.107 Sq. (in)    2.984 Sq. (in)    42.00 %

Pins  .......................... 557
Pins per Route Area  ........... 162.195 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 6, 9.843, 10, 20, 40
    Layer 2 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... 10, 20, 30, 40
    Layer 3 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... 5, 10, 20, 40
    Layer 4 is a signal layer
        Trace Widths  .......... 5, 10, 20, 40

Nets  .......................... 145
Connections  ................... 409
Open Connections  .............. 0
Differential Pairs  ............ 15
Differential Pair Names:   HDMI_CLKM   HDMI_CLKP
                           HDMI_D0M   HDMI_D0P
                           HDMI_D1M   HDMI_D1P
                           HDMI_D2M   HDMI_D2P
                           MDI_TRXN0   MDI_TRXP0
                           MDI_TRXN1   MDI_TRXP1
                           MDI_TRXN2   MDI_TRXP2
                           MDI_TRXN3   MDI_TRXP3
                           N16796096   N16796138
                           N16796098   N16796136
                           N17125621   N17125693
                           SATA_RXN   SATA_RXP
                           SATA_TXN   SATA_TXP
                           USB_HOST_DN   USB_HOST_DP
                           USB_OTG_DN   USB_OTG_DP
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 107.107 (in)

Trace Widths Used (th)  ........ 5, 6, 9.843, 10, 20, 30, 40
Vias  .......................... 281
Via Span  Name                   Quantity
   1-4    022VIA                 4
          022VIA_10              277

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 109
    Parts Mounted on Top  ...... 95
        SMD  ................... 91
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 14
        SMD  ................... 13
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 317
    Holes per Board Area  ...... 89.212 Holes/Sq. (in)
Mounting Holes  ................ 5

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0