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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        \\Proton\job\SolidRun\CuBox 2-Lower-v1.1\PCB\

Design Status Report: \\Proton\job\SolidRun\CuBox 2-Lower-v1.1\PCB\LogFiles\DesignStatus_09.txt

Sun Oct 13 12:39:22 2013

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DESIGN STATUS
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Board Size Extents  ............ 1.929 X 1.929 (in)
Route Border Extents  .......... 1.899 X 1.899 (in)
Actual Board Area  ............. 3.638 (in)
Actual Route Area  ............. 3.525 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    7.276 Sq. (in)    2.805 Sq. (in)    38.55 %

Pins  .......................... 502
Pins per Route Area  ........... 142.417 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 10, 20, 40
    Layer 2 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        GNDC
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 5

Nets  .......................... 142
Connections  ................... 363
Open Connections  .............. 298
Differential Pairs  ............ 14
Differential Pair Names:   HDMI_CLKM   HDMI_CLKP
                           HDMI_D0M   HDMI_D0P
                           HDMI_D1M   HDMI_D1P
                           HDMI_D2M   HDMI_D2P
                           MDI_TRXN0   MDI_TRXP0
                           MDI_TRXN1   MDI_TRXP1
                           MDI_TRXN2   MDI_TRXP2
                           MDI_TRXN3   MDI_TRXP3
                           N16796096   N16796138
                           N16796098   N16796136
                           SATA_RXN   SATA_RXP
                           SATA_TXN   SATA_TXP
                           USB_HOST_DN   USB_HOST_DP
                           USB_OTG_DN   USB_OTG_DP
                           
Percent Routed  ................ 17.91 %

Netline Length  ................ 70.041 (in)
Netline Manhattan Length  ...... 84.71 (in)
Total Trace Length  ............ 10.151 (in)

Trace Widths Used (th)  ........ 5, 10, 20, 40
Vias  .......................... 15
Via Span  Name                   Quantity
   1-4    022VIA                 4
          022VIA_10              11

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 86
    Parts Mounted on Top  ...... 74
        SMD  ................... 70
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 12
        SMD  ................... 11
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 51
    Holes per Board Area  ...... 14.018 Holes/Sq. (in)
Mounting Holes  ................ 5

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0