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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        H:\job\SolidRun\CuBox 2-Lower\PCB\

Design Status Report: H:\job\SolidRun\CuBox 2-Lower\PCB\LogFiles\DesignStatus_08.txt

Wed Jul 24 07:33:41 2013

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DESIGN STATUS
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Board Size Extents  ............ 1.93 X 1.93 (in)
Route Border Extents  .......... 1.9 X 1.9 (in)
Actual Board Area  ............. 3.64 (in)
Actual Route Area  ............. 3.52 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    7.28 Sq. (in)     2.65 Sq. (in)     36.43 %

Pins  .......................... 560
Pins per Route Area  ........... 158.87 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 10, 20, 20.08, 40
    Layer 2 is a Positive Plane Layer with nets
        GND
        VIN_5V0
        GNDC
        Trace Widths  .......... 20
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 5, 10, 20, 20.08, 60

Nets  .......................... 180
Connections  ................... 353
Open Connections  .............. 0
Differential Pairs  ............ 10
Differential Pair Names:   HDMI_CLKM   HDMI_CLKP
                           HDMI_D0M   HDMI_D0P
                           HDMI_D1M   HDMI_D1P
                           HDMI_D2M   HDMI_D2P
                           N16796096   N16796138
                           N16796098   N16796136
                           SATA_RXN   SATA_RXP
                           SATA_TXN   SATA_TXP
                           USB_HOST_DN   USB_HOST_DP
                           USB_OTG_DN   USB_OTG_DP
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 70.31 (in)

Trace Widths Used (th)  ........ 5, 10, 20, 20.08, 40, 60
Vias  .......................... 300
Via Span  Name                   Quantity
   1-4    022VIA_10              237
          VIA40_hole20           63

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 99
    Parts Mounted on Top  ...... 64
        SMD  ................... 60
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 35
        SMD  ................... 34
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 333
    Holes per Board Area  ...... 91.53 Holes/Sq. (in)
Mounting Holes  ................ 2

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0