=======================================================================
Expedition PCB - Pinnacle - Version 2009.0.369.456
=======================================================================

Job Directory:        H:\job\SolidRun\CuBox 2-Upper\PCB\

Design Status Report: H:\job\SolidRun\CuBox 2-Upper\PCB\LogFiles\DesignStatus_07.txt

Mon Jul 22 08:48:11 2013

=======================================================================
DESIGN STATUS
=======================================================================
Board Size Extents  ............ 1.6 X 1.72 (in)
Route Border Extents  .......... 1.56 X 1.68 (in)
Actual Board Area  ............. 1.86 (in)
Actual Route Area  ............. 1.74 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    3.71 Sq. (in)     2.01 Sq. (in)     54.07 %

Pins  .......................... 104
Pins per Route Area  ........... 59.91 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 10, 20, 40
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 5, 10, 20

Nets  .......................... 27
Connections  ................... 72
Open Connections  .............. 0
Differential Pairs  ............ 4
Differential Pair Names:   MDI_TRXN0   MDI_TRXP0
                           MDI_TRXN1   MDI_TRXP1
                           MDI_TRXN2   MDI_TRXP2
                           MDI_TRXN3   MDI_TRXP3
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 24.26 (in)

Trace Widths Used (th)  ........ 5, 10, 20, 40
Vias  .......................... 48
Via Span  Name                   Quantity
   1-4    022VIA_11              1
          022VIA_10              47

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 26
    Parts Mounted on Top  ...... 6
        SMD  ................... 1
        Through  ............... 5
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 20
        SMD  ................... 18
        Through  ............... 2
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 94
    Holes per Board Area  ...... 50.66 Holes/Sq. (in)
Mounting Holes  ................ 12

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0