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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        H:\job\SolidRun\CuBox 2\PCB\

Design Status Report: H:\job\SolidRun\CuBox 2\PCB\LogFiles\DesignStatus_06.txt

Mon Jul 15 11:27:17 2013

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DESIGN STATUS
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Board Size Extents  ............ 3.19 X 2.72 (in)
Route Border Extents  .......... 3.15 X 1.89 (in)
Actual Board Area  ............. 8.66 (in)
Actual Route Area  ............. 5.94 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    17.33 Sq. (in)    2.68 Sq. (in)     15.49 %

Pins  .......................... 561
Pins per Route Area  ........... 94.38 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... None.
    Layer 2 is a Positive Plane Layer with nets
        GND
        (Shield Area)
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... None.

Nets  .......................... 179
Connections  ................... 214
Open Connections  .............. 209
Differential Pairs  ............ 0
Percent Routed  ................ 2.34 %

Netline Length  ................ 122.95 (in)
Netline Manhattan Length  ...... 148.65 (in)
Total Trace Length  ............ 0 (in)

Trace Widths Used (th)  ........ None.
Vias  .......................... 57
Via Span  Name                   Quantity
   1-4    VIA40_hole20           57

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 35
    Parts Mounted on Top  ...... 31
        SMD  ................... 27
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 4
        SMD  ................... 3
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 60

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 92
    Holes per Board Area  ...... 10.62 Holes/Sq. (in)
Mounting Holes  ................ 4

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0