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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        D:\Job\SolidRun\2CUBE-v3\PCB\

Design Status Report: D:\Job\SolidRun\2CUBE-v3\PCB\LogFiles\DesignStatus_05.txt

Thu Aug 30 14:02:19 2012

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DESIGN STATUS
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Board Size Extents  ............ 3.189 X 2.717 (in)
Route Border Extents  .......... 3.145 X 1.89 (in)
Actual Board Area  ............. 8.664 (in)
Actual Route Area  ............. 5.944 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    17.328 Sq. (in)   7.871 Sq. (in)    45.42 %

Pins  .......................... 2119
Pins per Route Area  ........... 356.491 Pins/Sq. (in)

Layers  ........................ 8
    Layer 1 is a signal layer
        Trace Widths  .......... 4, 8, 10, 14, 15, 20, 30, 40, 50
    Layer 2 is a Positive Plane Layer with nets
        GND
        GND_B2
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 4, 10, 15, 20, 40
    Layer 4 is a Positive Plane Layer with nets
        V_1_CORE
        V_3.3
        V_3.3_B2
        V_5.0_HDMI_CONN
        VREF_DDR
        V_1.8_B2
        V_USB0
        GND_B2
        V_IN_B2
        V_1.5
        Trace Widths  .......... 15
    Layer 5 is a Positive Plane Layer with nets
        V_IN_B2
        V_1.5
        V_1.8
        V_1.8_A_HDMI
        V_1.8_RJ45_B2
        V_1.8_RTC
        V_1_CPU
        Trace Widths  .......... 15
    Layer 6 is a signal layer
        Trace Widths  .......... 4, 15, 20, 50
    Layer 7 is a Positive Plane Layer with nets
        GND
        GND_B2
        Trace Widths  .......... None.
    Layer 8 is a signal layer
        Trace Widths  .......... 4, 8, 10, 14, 15, 20, 25, 30, 35, 40

Nets  .......................... 355
Connections  ................... 1712
Open Connections  .............. 0
Differential Pairs  ............ 12
Differential Pair Names:   M_CLKOUTN0   M_CLKOUT0
                           M_CLKOUTN1   M_CLKOUT1
                           M_DQSN0   M_DQS0
                           M_DQSN1   M_DQS1
                           M_DQSN2   M_DQS2
                           M_DQSN3   M_DQS3
                           SATA_C_RX_N   SATA_C_RX_P
                           SATA_C_TX_N   SATA_C_TX_P
                           SRXN_1   SRXP_1
                           STXN_1   STXP_1
                           USB0_D_N   USB0_D_P
                           USB1_D_N   USB1_D_P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 256.892 (in)

Trace Widths Used (th)  ........ 4, 8, 10, 14, 15, 20, 25, 30, 35, 40, 50
Vias  .......................... 1140
Via Span  Name                   Quantity
   1-8    VIA20_hole14           18
          VIA18_hole8            1122

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 380
    Parts Mounted on Top  ...... 263
        SMD  ................... 253
        Through  ............... 10
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 117
        SMD  ................... 115
        Through  ............... 2
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 1224
    Holes per Board Area  ...... 141.274 Holes/Sq. (in)
Mounting Holes  ................ 19

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0